Due to the increasing advance of science and technology, digitized information processing means plays a more and more important role on our daily lives and business activities. Consequently, the data processing amount is too huge to be operated by using a simple data processing device, such as a computer system with a single processor and a local memory. In order to efficiently deal with a large quantity of data, a processing system involving a distributed shared memory (DSM) is developed for parallel data-processing and rapid data-sharing purpose for a remote node to access a local memory.
Please refer to FIG. 1, which is a schematic block diagram of a multi-processor computer architecture having a distributed shared memory (DSM). For example, a computer system with one or more processors can be considered as a DSM node. As shown in FIG. 1, the computer system is a multiprocessor computer architecture. In general, the computer system with a single processor can be consider as a DSM node, too. Processors 110 and 120 included in the DSM node are electrically connected to a memory control chip 130 via a system bus 160. By way of the memory control chip 130, the access operations between the processors 110, the processor 120 and a local memory 150 is controlled. The memory control chip 130 could be further electrically connected to other devices for basic input/output control and the task of the memory control chip 130 is executed by a north-bridge chip in a computer system.
The local memory 150 is divided into a plurality of local memory lines for storing data. When necessary, the processor 110 or 120 asserts a data access request to the memory control chip 130, thereby accessing data stored in the local memory lines via the memory control chip 130.
In a DSM system architecture, the data accessing/transferring communication among DSM nodes is controlled by DSM controllers. As shown in FIG. 1, the local DSM node 100 transmits/receives data to/from a remote DSM node via a DSM controller 140. The DSM controller 140 is electrically connected to the system bus 160 and to the memory control chip 130 via an internal bus 135.
As the processor 110 or 120 of the local node 100 accesses data stored in a memory line of a remote node, the DSM controller 140 communicates with the DSM controller (not shown) of the remote node to access data therein.
Since each node must shares its own memory lines with other nodes, a memory coherency directory is required for each node. The status of each memory line in a node is recorded in the memory coherency directory. When a remote node is going to access the local memory 150 in the local node 100, the memory coherency directory in the node 100 must be referred to check the status of the local memory 150 to decide how to access it by the remote node in order to make sure that the data accessed by the remote node is right.
Please refer to FIG. 2, which is a schematic diagram showing various status of a local memory line, including HOME, SHARED, GONE and WASH. The four kinds of status are described as follows.                HOME: The local memory is not accessed by any remote node.        SHARED: The local memory was accessed by a remote node and the data in the local memory line is not revised by the remote node.        GONE: The local memory was accessed by a remote node and the data in the local memory line was revised by the remote node.        WASH: The data in the local memory was revised by a remote node and was transmitted to the local node.        
The data revision procedures in the local memory line in response to the status will be described hereinafter. The initial status of the local memory line in the memory coherency directory is supposed to be HOME status. In HOME status, the processors in the local node can freely access data from the local memory line, and the data is exclusively stored in the local node. When a remote node asserts a “remote read line” command in HOME status of the local node, it indicates the remote node is going to read data from the local memory line. At meantime, the data in the local memory line is transmitted to the remote node. Accordingly, the memory status of the local memory line in the memory coherency directory will be changed from HOME to SHARED, as shown in path “1” of FIG. 2. Meanwhile, as the status of the local memory line is recorded in the memory coherency directory as SHARED status, the data in the local memory line is also stored in the remote node.
In SHARED status, when the local node asserts a “local read invalidate” or “local invalidate” signal, it indicates that the local node is going to revise the data in the local memory line. Therefore, the memory status of the local memory line in the memory coherency directory will change from SHARED to HOME, as shown as path “2”, in order that the processor(s) of the local node can freely access the data in the local memory line. Thus the data previously stored in the remote node will be out of date and invalidated.
In another case, when a remote node asserts a “remote rollout of shared copy” signal in SHARED status, it indicates the remote node abandons the data in the local memory copy. Under this circumstance, the memory status of the local memory line in the memory coherency directory also changes from SHARED to HOME, as shown as path “4”.
In further another case, when a remote node asserts a “remote invalidate” signal, it indicates the remote node is going to revise the data in the local memory line. Thus, the memory status of the local memory line in the memory coherency directory will change from SHARED to GONE, as shown as path “7”. GONE status indicates that the data in the local memory line is out of date, and the updated data supposed to be stored in the local memory line is stored in the remote node.
On the other hand, as shown as path “6”, when a remote node asserts a “remote read invalidate” signal in HOME status, it indicates that the remote node is going to read and revise the data in the local memory line, and the memory status of the local memory line in the memory coherency directory will change from HOME to GONE.
According to GONE status, when a remote node asserts a “remote rollout of modified copy” signal, it indicates that the remote node is going to release the revised data to the local memory line. The memory status of the local memory line in the memory coherency directory will change from GONE to HOME, as shown as path “8”. In other words, the revised data returns the local node.
Further, when the local node asserts a “local read line” or “local read invalidate” signal, it indicates that the local node is going to read the data in the local memory line and optionally revise the data after reading. Meanwhile, the memory status of the local memory line in the memory coherency directory will change from GONE to WASH, as shown as path “5”. According to WASH status, a transition state is indicated as that the data of the local memory line is being transferred from a remote node back to the local node.
Under WASH status, when the local node asserts a “completion of local read line” signal, it indicates that the local node is going to read rather than revise the data in the local memory line. At this moment, the memory status of the local memory line in the memory coherency directory will change from WASH to SHARED, as shown as path “9”. Then the data in the local memory line is allowed to be stored in both the local node and a remote node.
On the other hand, when the local node asserts a “completion of local read invalidate” signal, it indicates that the local node is going to read and revise the data in the local memory line. The memory status of the local memory line in the memory coherency directory will change from WASH to HOME, as shown as path “10”, to store the data only in the local node.
According to the above description, it is understood that the reading operations of a remote node can be coordinated according to the memory coherency directory which records therein the status of the local memory lines. The DSM controller of each node must maintain a memory coherency directory and the status recorded therein according to each memory line. As a remote node access the local memory line in the local node, the memory status of the memory line according to the memory coherency directory must be checked for deciding how to access the memory line in order to make sure that right data is accessed by the remote node.
Please refer to FIG. 1 again. When a remote node is going to read data in the local memory line, the DSM controller 140 in the local node 100 will assert a “system bus transaction” signal to realize the position of the data in the local memory line.
If the data is stored in the cache memory of the processor 110 or 120, the processor 110 or 120 will assert “hit” command to transmit the data to the system bus 160, and write the data back to the local memory 150 via the memory control chip 130. Meanwhile, the DSM controller 140 receives the data in the local memory line via the system bus 160, and transmits the data to a remote node. The current status of the local memory line defined in the memory coherency directory is the SHARED status.
If the data is stored in the local memory 150, the processor 110 or 120 will not assert “hit” command. Under this circumstance, the DSM controller 140 will request the memory control chip 130 to transmit thereto the data in the local memory line via the internal bus 135, and then transmit the data to a remote node. The current status of the local memory line defined in the memory coherency directory is SHARED status.
When a remote node requests to read data from the local memory line in HOME status, the position of the data in the local memory line cannot be acquired by the remote node. For example, the data may be stored in the local memory or cache memory or both. Therefore, the DSM controller 140 has to assert the “system bus transaction” command to realize the position of the data in the local memory line. Even in the case that the data has been stored in the local memory, the DSM controller 140 still needs to assert the “system bus transaction” command to inquire the position of the data in the local memory line. Therefore, a heavy burden is added to the system bus 160, and the time period required to read data from the local memory line is prolonged.